Semiconductor device and manufacturing method thereof

ABSTRACT

A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

[0001] This is a continuation of U.S. Ser. No. 09/449,834, filed Nov.26, 1999, which, in turn, is a continuation of U.S. Ser. No. 08/822,833,filed Mar. 21, 1997, and the disclosures of which are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention concerns a semiconductor integrated circuitdevice technique and, more in particular, it relates to a usefultechnique to be applied to portable equipment, such as portabletelephones and handy type personal computers, for which there is astrong trend toward reducing the size, the weight and the thickness ofthe product.

[0003] Recently, a trend toward reducing the size, the weight and thethickness of the product has become vigorous for electronic equipmentalong with an improved function and performance. This is largely due toa rapid increase in the use of personal equipment, such as personaltelephones or handy type personal computers in recent years. Further,man-machine interface functions have been increased in personallymanipulated equipment, for which easy handlability and operability havebeen considered increasingly important. It is considered that the trendwill become more and more conspicuous in expected regular multimediaareas.

[0004] Under such circumstances, development for increasing the densityand the degree of integration of semiconductor chips has progressedcontinuously, however the size and the number of electrodes of thesemiconductor chips have increased, while the size of the packages havealso increased rapidly. Accordingly, narrowing of the pitch of terminalleads has been promoted for facilitating the size reduction of thepackages, which makes mounting of the package more difficult.

[0005] In view of the above, it has been proposed in recent years toprovide high density packages with super-multiple pins having the samearea as that of the semiconductor chips, and such packaging techniquesare mentioned, for example, in various publications, such as “NikkeiMicrodevice” p 98-p 102, issued on May 1, 1994, “Nikkei Microdevice” p96-p 97, issued on Feb. 1, 1995 by Nikkei BPCO and “ElectronicMaterial”, p 22-p 28, issued on Apr. 1, 1995 (Heisei 7) by KogyoChosakai. One example of the structures produced such packagingtechniques, for example, as described in FIG. 6 of the “ElectronicMaterial” publication, has a package structure in which a flexiblewiring substrate is disposed by way of an elastomer (elastic material)on the surface of a semiconductor chip, leads on one end of wirings ofthe flexible wiring substrate are electrically connected with bondingpads on the surface of the semiconductor chip, and bump lands on theother end of the wirings of the flexible wiring substrate areelectrically connected with the solder bumps.

[0006] The package structure has an outer size about equal to or greaterthan that of a semiconductor chip by the size of a protection frameoptionally attached to the periphery of the chip, for which a flexiblewiring substrate formed with solder bumps is used. The wiring pattern ofthe wiring substrate is made of a Cu foil having a Au plating on oneside, the top ends of which to be connected with the pad of the chipconstitute a lead pattern which is only composed of Au as a result ofetching the Cu foil. In this structure, the flexible wiring substrate isbonded by an elastomer on the surface of the semiconductor chip and thenthe Au leads are connected with the bonding pads of the semiconductorchip.

SUMMARY OF THE INVENTION

[0007] In a study made by the present inventor of the package structureas described above, the following problems were recognized. For example,since the flexible wiring substrate in the package structure describedabove has a structure typically represented by a TCP (Tape CarrierPackage) in which a Cu wiring pattern is formed on the surface of apolyimide tape, and an elastomer is formed to the wiring substrate onthe side of the wiring surface, it is difficult to mount the elastomeruniformly and stably because of unevenness of the wiring pattern on theflexible wiring substrate. That is, there exist such problems that voidsnot filled with the elastomer are formed near both sides of theprotrusions of the wiring pattern upon coating or appending theelastomer on the flexible wiring substrate, and the step of bonding thesemiconductor chip can not be conducted stably since the size and theshape of the elastomer are not stable.

[0008] Further, bump electrodes are formed on the wiring substrate onthe side of the tape. That is, a bump electrode is connected with thewirings by way of a through hole formed in the tape. Since the thicknessof the tape is relatively large, for example, as much as 50 μm, if thepitch between the bump electrodes is smaller than the thickness of thetape, the aspect ratio of the through hole is increased to bring about aconcern that the bump electrode and the wiring will not be connected.Accordingly, there is a concern that an increase in the number of pinsof the package may be restricted.

[0009] In view of the above, an object of the present invention is toprovide a semiconductor integrated circuit device capable of mounting anelastic structural material to a wiring substrate stably with a highaccuracy and making the bonding step of a semiconductor chip stable,thereby enabling assembling with a high yield.

[0010] Another object of the present invention is to provide a techniquefor promoting an increase in the number of pins in a package.

[0011] An object of the present invention is to provide a semiconductorintegrated circuit device capable of obtaining excellent electricalproperties in view of noise resistance by the adoption of a multiplewiring layer structure.

[0012] An object of the present invention is to prevent wiring frombecoming contaminated ingredients of an elastic structural material.

[0013] An object of the present invention is to prevent a semiconductorchip from being damaged, improve the reliability of the semiconductorchip, as well as prevent connection failure between an elasticstructural material and the semiconductor chip, worsening of theflatness of the wiring substrate and lowering of reliability.

[0014] An object of the present invention is to eliminate a requirementfor a soft-modified special wire bonder and to effect a shortening ofthe contact time upon bonding by further simplifying the trace of thebonding tool.

[0015] An object of the present invention is to solve a problemconcerning disconnection of wirings.

[0016] An object of the present invention is to reduce any damage to apassivation layer or a semiconductor chip therebelow and further improvethe bondability by preventing contamination of the wirings.

[0017] An object of the present invention is to increase the bondingstrength between wirings and a substrate material and obtain a stablenotch cutting performance.

[0018] An object of the present invention is to suppress warp of awiring substrate and improve bondability with a bonding material, so asto constitute a package of excellent moisture proofness and reliability.

[0019] An object of the present invention is to improve thegroove-fillage capability of an elastic structural material, capable ofincreasing the strength of a metal mask, by using a plurality of oneside bridging portions, and further improving the groove-fillagecapability by the formation of a stopping dam for sealant flow

[0020] An object of the present invention is to improve the bondabilityand prevent damage to a semiconductor chip in an inner lead bondingtechnique.

[0021] An object of the present invention is to form a suitable S-shapedconfiguration with no return of a bonding tool but by merely driving thebonding tool vertically using a wiring design which takes intoconsideration a bending stress ratio.

[0022] An object of the present invention is to reduce the occurrence ofcracks in wirings per se and moderate bonding damage to a semiconductorchip.

[0023] An object of the present invention is to suppress bleeding of lowmolecular weight ingredients of an elastic structural material andfurther avoid a disadvantage involving the creation of voids uponforming the elastic structural material by surface flattening.

[0024] An object of the present invention is to improve the fabricationaccuracy for hole diameter for connection of a bump electrode in amethod of manufacturing a semiconductor integrated circuit.

[0025] An object of the present invention is to provide a technique forforming a semiconductor package which is capable of bonding bumpelectrodes more satisfactorily, reducing the pitch of the bumpelectrodes and which provides output terminals at a higher density in amethod of manufacturing a semiconductor integrated circuit device.

[0026] These and other objects, as well as novel features of the presentinvention will become apparent by consideration of the descriptions inthe specification with reference to the accompanying drawings.

[0027] Among the features disclosed in the present application, asummary of typical examples will be explained simply as follows.

[0028] That is, one of the semiconductor integrated circuit devicesaccording to the present invention provides a package structure appliedto a semiconductor integrated circuit device in which a wiring substrateis disposed by way of an elastic structural material on a main surfaceof a semiconductor chip, lead portions on one end of the wirings of thewiring substrate are electrically connected with external terminals onthe main surface of the semiconductor chip, and land portions on theother end of the wirings of the wiring substrate are electricallyconnected with bump electrodes, wherein the wiring substrate has wiringsformed on the main surface of a substrate base material (tape), and anelastic structural material is disposed opposite to the main surface ofthe substrate base material.

[0029] Further, the bump electrodes are formed on the side of thewirings.

[0030] Further, the bump electrodes are connected with the wirings eachby way of a through hole disposed in an insulation film formed on thewirings and having a thickness smaller than that of the wiring basematerial.

[0031] Further, the external terminals of the semiconductor chip aredisposed at a central portion or at an outer circumferential portion ofthe semiconductor chip, and the bump electrodes connected to theexternal terminals of the semiconductor chip by way of the wirings ofthe wiring substrate are disposed to the inside, outside or in bothregions inside and outside with respect to the outer circumference ofthe semiconductor chip.

[0032] Further, in a semiconductor integrated circuit device of thepresent invention, the size of the end of the elastic structural memberof the semiconductor chip on the side of the externals terminal and theend of the substrate base material of the wiring substrate is determinedbased on the ingredients of the elastic structural material.

[0033] Further, in a semiconductor integrated circuit device of thepresent invention, a distance M2 between the end of the substrate basematerial of the wiring substrate and the end of the elastic structuralmaterial on the outer circumferential side of the semiconductorintegrated circuit device, and a distance M1 between the end of thesemiconductor chip and the end of the substrate base material aredetermined within a range capable of satisfying the relationship:

M1>M2>0

[0034] Further, in a semiconductor integrated circuit device of thepresent invention, the wirings of the wiring substrate are formed tosuch a shape that a portion fixed with the substrate base material ofthe wiring substrate and a top end portion connected to the externalterminals of the semiconductor chip are displaced at least by more thanthe width of the wirings.

[0035] Further, in a semiconductor integrated circuit device of thepresent invention, the wirings of the wiring substrate are formed as acantilever structure fixed at one side to the substrate base material ofthe wiring substrate.

[0036] Further, in a semiconductor integrated circuit device of thepresent invention, the size of the end of an opening in a surfaceprotection film on the semiconductor chip is determined within such arange that the wirings do not interfere with the surface protection filmat least on the side thereof on which a bonding tool is driven down.

[0037] Further, in a semiconductor integrated circuit device of thepresent invention, the wirings of the wiring substrate are formed suchthat an effective area of a wiring portion of the wiring on the side ofthe notch terminal end is made larger. Particularly, the wiring portionon the side of the notch terminal end is connected with an opposed landportion of the wirings, or is extended longitudinally or laterally in avacant region of the wirings, or adjacent wirings are connected witheach other.

[0038] Further, in a semiconductor integrated circuit device of thepresent invention, the elastic structural material is formed within arange greater over the entire circumference at least by more than thewidth of a protrusion at the outer circumferential portion formed in theelastic structural material.

[0039] Further, in a semiconductor integrated circuit device of thepresent invention, when the elastic structural material is formed in twoparts so as not to be bonded on the external terminals of thesemiconductor chip, each of the ends of spaces to which the dividedelastic structural materials are opposed is formed in a groove-shape.Particularly, a plurality of grooves are formed at each of the ends ofthe elastic structural material, or a stepping dam for sealant flow ispreviously formed during a sealing step.

[0040] Further, in a semiconductor integrated circuit device of thepresent invention, the connection structure between the externalterminals of the semiconductor chip and the wirings of the wiringsubstrate are formed by previously forming stud bumps on the externalterminals of the semiconductor chip, and the external terminals of thesemiconductor chip and the wirings of the wiring substrate are connectedby way of the stud bumps.

[0041] Further, in a semiconductor integrated circuit device of thepresent invention, the connection structure between the externalterminals of the semiconductor chip and the wiring substrate is formedby previously supplying solder so as to surround the wirings of thewiring substrate and the external terminals of the semiconductor chip,and the external terminals of the semiconductor chip are connected byway of the solder.

[0042] Further, in a semiconductor integrated circuit device of thepresent invention, the connection structure between the externalterminal of the semiconductor chip and the wirings of the semiconductorsubstrate are formed by connecting the wirings of the wiring substrateand the external terminals of the semiconductor chip by way of studbumps by using stud bumps of solder or Au ball so as to surround thewirings of the wiring substrate from above.

[0043] Further, in a semiconductor integrated circuit device of thepresent invention, the connection structure between the externalterminals of the semiconductor chip and the wirings of the wiringsubstrate are formed by connecting the wirings of the wiring substrateand the external terminals of the semiconductor chip by using Al, solderor Au wire.

[0044] Further, in a semiconductor integrated circuit device of thepresent invention, the wiring structure of the wiring substrate isformed by narrowing the lateral size of the wirings from the end of thesubstrate base material of the wiring substrate to the top end of thewirings, such that the bending stress ratio a is represented by:

α=σ1/σ0

[0045] where σ0 is bending strength caused at the end of the substratebase material and σ1 is maximum stress caused at an intermediate portionbetween the end of the substrate base material and the top end of thewirings, and wherein the lateral size is made constant particularly froma predetermined position, and the size and the shape of the wirings aredetermined such that the bending stress ratio a is from 1.2 to 1.5 in acase where the bending stress ratio α is represented by the followingformula:

α=b1×(L2−L1)/(b2×L2)

[0046] in which L1 is a taper length, L2 is a wiring length, b1 is ataper width and b2 is a wiring width.

[0047] Further, in a semiconductor integrated circuit device of thepresent invention, the wiring structure of the wiring substrate isformed by using an electroconductive material as a core material andapplying Au plating on the surface.

[0048] Further, the wiring structure of the wiring substrate is formedby using Cu as a core material, applying Au plating on the surface andmaking at least one end connected with the external electrodes of thechip into a S-shaped configuration.

[0049] Further, in a semiconductor integrated circuit device of thepresent invention, a flattening insulation film is formed on the wiringsubstrate on the side of the wirings and an elastic structural materialis disposed on the insulation film.

[0050] Further, a method of manufacturing a semiconductor integratedcircuit device according to the present invention comprises a step offorming an elastic structural material on the rear face of a wiringsubstrate (tape side) in which wirings are formed on the substrate basematerial (tape), a step of bonding a semiconductor chip to the surfaceof the elastic structural material so as to oppose the wiring substrate,a step of connecting one end of the wirings to the external terminals ofthe semiconductor chip, a step of forming an insulation film thinnerthan the substrate base material on a main surface of the wirings, astep of forming openings to the insulation film each at a positioncorresponding to the other end of the wirings to be Joined with the bumpelectrodes, and a step of forming the bump electrodes being joined tothe other end of the wirings by way of the wirings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0051]FIG. 1 is a plan view illustrating a semiconductor integratedcircuit device which represents an Embodiment 1 of the presentinvention;

[0052]FIG. 2 is a cross sectional view taken along line A-A′ in FIG. 1of the Embodiment 1 according to the present invention;

[0053]FIG. 3 is a plan view illustrating the state of mounting thesemiconductor integrated circuit device in the Embodiment 1 according tothe present invention to a mounting substrate;

[0054]FIG. 4 is a cross sectional view illustrating the state ofmounting the semiconductor integrated circuit device in the Embodiment 1according to the present invention to a mounting substrate;

[0055]FIG. 5 is a flow chart illustrating the steps of assembling thesemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0056]FIG. 6 is a cross sectional view of a main portion of thesemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0057]FIG. 7 is a cross sectional view of a main portion for comparativeexplanation of the semiconductor integrated circuit device of theEmbodiment 1 according to the present invention and a semiconductorintegrated circuit device studied by the present inventor;

[0058]FIG. 8 is a cross sectional view of a main portion illustratingboth face wirings as a modified embodiment of a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

[0059]FIG. 9 is a plan view illustrating a window opening portion of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0060]FIG. 10 is a cross sectional view corresponding to the windowopening in FIG. 9;

[0061]FIG. 11 is a cross sectional view for explaining the size of awindow opening and an edge portion of the semiconductor chip in asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0062]FIG. 12 is a cross sectional view illustrating a concave shape ofan elastomer after printing of a semiconductor integrated circuit devicein the Embodiment 1 according to the present invention;

[0063]FIG. 13 is a cross sectional view illustrating a tape warpingafter appending a semiconductor chip in a semiconductor integratedcircuit device of the Embodiment 1 according to the present invention;

[0064]FIG. 14 is a plan view illustrating a planer S-shaped lead of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0065]FIG. 15 is a cross sectional view as seen in the direction ofarrow B in FIG. 14 of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0066]FIG. 16 is a cross sectional view as seen in the direction ofarrow A in FIG. 14 in a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0067]FIG. 17 is a cross sectional view illustrating a trace of abonding tool upon forming a standard S-shaped lead in a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

[0068]FIG. 18 is a cross sectional view illustrating a trace of abonding tool upon forming a planer S-shaped lead in a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

[0069]FIG. 19 is a plan view for explaining a notch lead and a beam leadof a semiconductor integrated circuit device in the Embodiment 1according to the present invention;

[0070]FIG. 20 is a plan view illustrating a notch lead at the portion Ain FIG. 19 of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0071]FIG. 21 is a plan view illustrating a beam lead of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

[0072]FIG. 22 is a cross sectional view illustrating a lead bondingportion of a semiconductor integrated circuit device in the Embodiment 1according to the present invention;

[0073]FIG. 23 is a plan view illustrating a lead bonding portion of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0074]FIG. 24 is a cross sectional view illustrating, in an enlargedscale, a landing position of a tool in the portion A in FIG. 22, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0075]FIG. 25 is a cross sectional view illustrating a bonding portionimproved for the size of a passivation opening, of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

[0076]FIG. 26 is a plan view illustrating a bonding portion for leadsextending in both directions of a semiconductor integrated circuitdevice in the Embodiment 1 according to the present invention;

[0077]FIG. 27 is a plan view illustrating standard anchor wirings, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0078]FIG. 28 is a plan view illustrating improved anchor wirings, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0079]FIG. 29 is a perspective view illustrating a structure of astandard elastomer, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0080]FIG. 30 is a perspective view illustrating a state of appending asemiconductor chip at a standard elastomer, of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

[0081]FIG. 31 is a perspective view illustrating a structure of a wideelastomer, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0082]FIG. 32 is a perspective view illustrating a state of appending asemiconductor chip at a wide elastomer, of a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

[0083]FIG. 33 is a cross sectional view illustrating a state ofappending a semiconductor chip at a wide elastomer, of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

[0084]FIG. 34 is a perspective view illustrating a structure of thestandard elastomer after appending a semiconductor chip, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0085]FIG. 35 is a cross sectional view illustrating a structure of astandard elastomer after appending the semiconductor chip, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0086]FIG. 36 is a perspective view illustrating a structure of a wideelastomer after appending the semiconductor chip, of a semiconductorintegrated circuit device in the Embodiment 1 according to the presentinvention;

[0087]FIG. 37 is a cross sectional view illustrating a structure of awide elastomer after appending the semiconductor chip, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0088]FIG. 38 is a cross sectional view illustrating a concept of metalmask printing, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0089]FIG. 39 is a plan view illustrating a metal mask of a standardelastomer, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0090]FIG. 40 is a plan view illustrating a metal mask of a wideelastomer, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0091]FIG. 41 is a plan view illustrating a printed shape for aplurality of suspended wide elastomers, of a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

[0092]FIG. 42 is a plan view illustrating a potting position forgroove-fillage of a wide elastomer, of a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

[0093]FIG. 43 is a cross sectional view illustrating a bonding portionby a standard lead bonding, of a semiconductor integrated circuit devicein the Embodiment 1 according to the present invention;

[0094]FIG. 44 is a cross sectional view illustrating a bonding portionby using stud bumps, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0095]FIG. 45 is a cross sectional view illustrating a lead connectionby using solder, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0096]FIG. 46 is a plan view illustrating a lead connection usingsolder, of a semiconductor integrated circuit device in the Embodiment 1according to the present invention;

[0097]FIG. 47 is a cross sectional view illustrating a lead connectionby using solder or Au ball, of a semiconductor integrated circuit devicein the Embodiment 1 according to the present invention;

[0098]FIG. 48 is a perspective view illustrating a lead connection byusing solder or Au ball, of a semiconductor integrated circuit device inthe Embodiment 1 according to the present invention;

[0099]FIG. 49 is a cross sectional view illustrating a lead connectionby using Al or soldering wire, of a semiconductor integrated circuitdevice in the Embodiment 1 according to the present invention;

[0100]FIG. 50 is a cross sectional view illustrating a lead connectionby using an Au wire, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0101]FIG. 51 is a perspective view for explaining a lead design, of asemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0102]FIG. 52 is a perspective view illustrating modification of a leadafter bonding, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0103]FIG. 53 is chart illustrating a relationship between a lead sizeand a bending stress ratio, of a semiconductor integrated circuit devicein the Embodiment 1 according to the present invention;

[0104]FIG. 54 is a cross sectional view illustrating a connectionportion of lead connection, of a semiconductor integrated circuit devicein the Embodiment 1 according to the present invention;

[0105]FIG. 55 is an enlarged cross sectional view illustrating a leadbent portion, of a semiconductor integrated circuit device in theEmbodiment 1 according to the present invention;

[0106]FIG. 56 is an enlarged cross sectional view illustrating aNi-platingless lead bent portion, of a semiconductor integrated circuitdevice in the Embodiment 1 according to the present invention;

[0107]FIG. 57 is an enlarged cross sectional view illustrating a leadpress contact portion, of a semiconductor integrated circuit device inthe Embodiment 1 according to the present invention;

[0108]FIG. 58 is an enlarged cross sectional view illustrating aNi-platingless lead press contact portion, of a semiconductor integratedcircuit device in the Embodiment 1 according to the present invention;

[0109]FIG. 59 is a cross sectional view illustrating a structure of asemiconductor integrated circuit device in an Embodiment 2 according tothe present invention;

[0110]FIG. 60 is a perspective view illustrating a structure of asemiconductor integrated circuit device in the Embodiment 2 according tothe present invention;

[0111]FIG. 61 is a plan view, as viewed from the rear face of asemiconductor chip, of a semiconductor integrated circuit device in theEmbodiment 3 according to the present invention;

[0112]FIG. 62 is a plan view illustrating a semiconductor integratedcircuit device in the Embodiment 3 according to the present invention;

[0113]FIG. 63 is a cross sectional view illustrating a semiconductorintegrated circuit device in the Embodiment 3 according to the presentinvention;

[0114]FIG. 64 is an enlarged cross sectional view illustrating a portionA in FIG. 63, of a semiconductor integrated circuit device in theEmbodiment 3 according to the present invention;

[0115]FIG. 65 is a plan view for explaining a wiring structure of awiring substrate, of a semiconductor integrated circuit device in theEmbodiment 3 according to the present invention;

[0116]FIG. 66 is a plan view, as viewed from the rear face of asemiconductor chip, of a semiconductor integrated circuit device as anEmbodiment 4 according to the present invention;

[0117]FIG. 67 is a plan view illustrating a semiconductor integratedcircuit device in the Embodiment 4 according to the present invention;

[0118]FIG. 68 is a cross sectional view illustrating a semiconductorintegrated circuit device in the Embodiment 4 according to the presentinvention;

[0119]FIG. 69 is an enlarged cross sectional view illustrating a portionA in FIG. 68, of a semiconductor integrated circuit device in theEmbodiment 4 according to the present invention;

[0120]FIG. 70 is a plan view for explaining a wiring structure of awiring substrate, of a semiconductor integrated circuit device in theEmbodiment 4 according to the present invention;

[0121]FIG. 71 is a plan view, as viewed from the rear face of asemiconductor chip, of a semiconductor integrated circuit device in theEmbodiment 5 according to the present invention;

[0122]FIG. 72 is a plan view illustrating a semiconductor integratedcircuit device in the Embodiment 5 according to the present invention;

[0123]FIG. 73 is a cross sectional view illustrating a semiconductorintegrated circuit device in the Embodiment 5 according to the presentinvention;

[0124]FIG. 74 is an enlarged cross sectional view illustrating a portionA in FIG. 73, of a semiconductor integrated circuit device in theEmbodiment 5 according to the present invention;

[0125]FIG. 75 is a plan view for explaining a wiring structure of awiring substrate, of a semiconductor integrated circuit device in theEmbodiment 5 according to the present invention;

[0126]FIG. 76 is a cross sectional view illustrating the modified shapeof the lead in accordance with the bending stress ratio in a comparativeexplanation between the semiconductor integrated circuit device in theEmbodiment 1 according to the present invention and the semiconductorcircuit device studied by the present inventors;

[0127]FIG. 77 is a cross sectional view illustrating the modified shapeof the lead in accordance with the bending stress ratio, of thesemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0128]FIG. 78 is a cross sectional view illustrating the modified shapeof the lead in accordance with the bending stress ratio, of thesemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0129]FIG. 79 is a cross sectional view illustrating the modified shapeof the lead in accordance with the bending stress ratio, of thesemiconductor integrated circuit device in the Embodiment 1 according tothe present invention;

[0130]FIG. 80 is a cross sectional view illustrating the modified shapeof the lead in accordance with the bending stress ratio, of thesemiconductor integrated circuit device in the Embodiment 1 according tothe present invention; and

[0131]FIG. 81 is a cross sectional view illustrating a modified exampleof a package structure, of the semiconductor integrated circuit devicein the Embodiment 1 according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0132] The present invention will be described more specifically by wayof preferred embodiments with reference to the drawings.

Embodiment 1

[0133]FIG. 1 is a plan view illustrating a semiconductor integratedcircuit device representing an Embodiment 1 according to the presentinvention, FIG. 2 is a cross sectional view taken along line A-A′ inFIG. 1, FIG. 3 and FIG. 4 are a plan view and a cross sectional viewillustrating a state of mounting a semiconductor integrated circuitdevice to a mounting substrate, FIG. 5 is a flow chart illustrating astep of assembling a semiconductor integrated circuit device, and FIG. 6to FIG. 58 and FIG. 76 to FIG. 81 are views for comparative explanationbetween the feature of the semiconductor integrated circuit devicerepresenting the Embodiment 1 of the present invention and asemiconductor integrated circuit device representing a comparativeexample studied by the present inventor. At first, an explanation willbe given as to the constitution of a semiconductor integrated circuitdevice of an Embodiment 1 with reference to FIG. 1 and FIG. 2.

[0134] The semiconductor integrated circuit device representingEmbodiment 1 of the present invention is in the form of a 40 pin ballgrid array type semiconductor package, comprising a semiconductor chip 1having a plurality of semiconductor elements and a plurality of bondingpads formed on a main surface, and an elastomer 2 (elastic structuralmaterial) bonded on the main surface of the semiconductor chip exceptingfor the portions forming the bonding pads, a flexible wiring substrate 3(wiring substrate) formed with wirings connected at one end to thebonding pads of the semiconductor chip 1, a solder resist 4 (insulationfilm) formed on a main surface of the flexible wiring substrate 3, andbumps 5 (bump electrodes) formed on a main surface of the solder resist4 and connected to the other end of the wirings by way of openings inthe solder resist 4, to constitute a package structure in which thebonding portion of the semiconductor chip 1 is covered by a sealant 6,such as a resin.

[0135] The semiconductor chip 1 has, for example, a center pad structureas shown in FIG. 1 in which a plurality of bonding pads 7 (externalterminals) are formed in one row at a central portion in thelongitudinal direction, and the bonding pads are arranged at non-uniformintervals. Predetermined integrated circuits, such as memory circuitsand logic circuits, are formed in the semiconductor chip 1, for example,on a semiconductor substrate, such as made of silicon, and the bondingpads 7 made of a material such as Al are disposed as the externalterminals for such circuits.

[0136] The elastomer 2 is made of an elastic material, for example, asilicone resin, which is formed on the main surface of the semiconductorchip 1, being bisected longitudinally of the chip 1 to provide theportion formed with the bonding pads 7, and is bonded to the mainsurface of the chip 1 by way of the adhesive 8. The elastomer 2 isprovided for moderating stress concentration on the soldering bumps 5mainly caused by the difference in the heat expansion coefficients ofthe semiconductor chip 1 and the package mounting substrate.

[0137] The flexible wiring substrate 3 comprises, for example, as shownin FIG. 2, a tape 9 as a basic material of the flexible wiring substrate3 (substrate base material) and wirings 10 bonded on the main surface ofthe tape 9 by an adhesive 9′, in which leads 11 on one end of thewirings 10 are connected to the bonding pads 7 of the semiconductor chip1, and bump lands 12 on the other end are connected with the solderingbumps 5. In the flexible wiring substrate 3, the rear face of the tape 9(on the side opposite to the surface formed with the wirings 10) isbonded to the elastomer 2, and the solder resist 4 is formed on the mainsurface of the wirings 10.

[0138] The tape 9 constituting the flexible wiring substrate 3 is madeof a material, for example, a polyimide resin, and a material such as Cuis used as the core material for the wiring 10. A portion of the lead 11serving as one end of the wiring 10 is formed with an Ni plating layerso as to cover the surface of the core material, and an Au plating layeris formed further so as to cover the surface of the Ni plating layer.

[0139] The solder resist 4 is made of an insulation material, such as alight sensitive epoxy resin, and the solder bumps 5 are formed on themain surface of the wirings 10 of the flexible wiring substrate 3 by wayof the openings in the solder resist 4 for a predetermined range of thewirings 10, except for the connection portion connected to the bumplands.

[0140] The soldering bumps 5 are made of a material, for example, aPb(560%)—Sn(40%) solder or an alloyed solder mainly composed of Pb—Sn,and is connected to the bump lands 12 of the wirings 10 constituting theflexible wiring substrate 3. The solder bumps 5 are arranged in two rowsin the regions on both side of the bonding pads 7 of the semiconductorchip 1.

[0141] The thus constituted semiconductor integrated circuit device ismounted, for example, as shown in FIG. 3 and FIG. 4, as a semiconductorintegrated circuit device of a chip size package 13, for example, aDRAM, together with a semiconductor integrated circuit device of QFPtype package 14, onto a mounting substrate 15, which is made, forexample, of glass or epoxy, on a memory card and can be retractablymounted with respect to portable equipment, such as a portable telephoneor a handy type personal computer by way of external connectionterminals 16.

[0142] For the function of the Embodiment 1 of the present invention, anoutline of the steps of assembling the semiconductor package will beexplained on the basis of the process flow shown in FIG. 5.

[0143] At first, before assembling the semiconductor package, wirings 10are formed on the tape 9, the flexible wiring substrates having theleads 11 formed by etching a portion of the wirings 10. Further, theelastomer 2, the semiconductor chip 1 formed with predeterminedintegrated circuits and provided with the bonding pads 7 as externalterminals, the sealant 6, and flux and solder forming the solder balls17 are provided.

[0144] The flexible wiring substrate 3 can be prepared, for example, astypically represented by the technique of a TAB (Tape Automatic Bonding)tape, by bonding a thin metal foil such as Cu on a tape 9 made of apolyimide resin by means of an adhesive, forming a required pattern byphotoresist on the metal foil using a photographic technique, thenforming a desired wiring pattern 10 by etching (including also leads 11)and, further, applying Ni—Au plating treatment to the surface thereof,for example, by an electric field plating method.

[0145] Then, for example, the elastomer 2 is formed by printing to athickness of 50 to 150 μm on the tape 9 of the flexible wiring substrate3, and a silicone type adhesives 8 is coated and printed on the surfaceof the elastomer 2 (steps 501, 509). The elastomer 2 is not alwaysprinted, but an elastomer previously formed into a film-shape may be cutinto a predetermined shape and bonded to the rear face of the tape 9 bymeans of the adhesive 8.

[0146] Further, the leads 11 at one end of the wirings 10 of theflexible wiring substrate 3 and the bonding pads 7 of the semiconductorchip 1 are aligned such that their relative positions coincide with eachother, and the semiconductor chip 1 is appended by adhesion to theelastomer 2 printed on the tape 19 of the flexible wiring substrate 3(step 503).

[0147] Then, they are turned upside down in a state where thesemiconductor chip 1 and the tape 9 of the wiring substrate 3 areappended by way of the elastomer 2, the semiconductor chip 1 and thetape 9 of the flexible wiring substrate 3 in a state appended by way ofthe elastomer 2 are turned upside down in the lead bonding step, thelead 11 is driven down on the bonding pad 7 of the semiconductor chip 1while being deformed into a S-shaped configuration by a bonding tool 18,as shown by the cross section in FIG. 2, and the lead 11 and the bondingpad 7 are connected, for example, by a method of supersonic thermalpress bonding (step 504).

[0148] Successively, in the sealing step, the lead bonding portion ofthe bonding pad 7 of the semiconductor chip 1 and the lead 11 of theflexible wiring substrate 3 are resin encapsulated, for example, bycoating a sealant 6, such as an epoxy resin, from a dispenser 19 tothereby enhance the reliability at the junction portion between thesemiconductor chip 1 and the flexible wiring substrate 3 (step 505).

[0149] Subsequently, in the cutting step for the flexible wiringsubstrate 3, the outer edge portion of the tape 9 is cut along aposition somewhat outside the edge of the semiconductor chip 1, to forma package outer shape of CSP (Chip Size Package or Chip Scale Package)(step 506).

[0150] Then, in the bump attaching step of the solder bump 5, the bump 5is formed by joining a solder ball 17 to the corresponding bump land 12of the wirings 10 of the flexible wiring substrate 3 to form the bump 5and, finally, by way of the selection and marking, the step ofassembling the semiconductor package in the Embodiment 1 according tothe present invention is finished (step 507, 508).

[0151] In the step of assembling the semiconductor package, the order ofthe tape cutting step (step 506) and the bump attaching step (step 507)may be reversed.

[0152] Thus, the Embodiment 1 has a semiconductor package structure inwhich bonding pads 7 are arranged concentrically in one row along acentral portion of the semiconductor chip 1, and the solder bumps 5 aredisposed at the inside of the outer circumference of the semiconductorchip 1 connected by way of the wirings 10 of the flexible wiringsubstrate from the bonding pads 7.

[0153] Now, the feature of the package structure for the semiconductorintegrated circuit device of the Embodiment 1 will be explained bycomparison with a package structure formed by a technique studied by thepresent inventor including the structure and the process with referenceto FIG. 6 to FIG. 58 successively.

[0154] 1. Surface Wiring Structure (a structure in which the elastomeris formed on the wiring substrate on the side of the tape and the bumpelectrodes are formed on the side of the wirings).

[0155] To assist in providing technical explanation of the surfacewiring structure, FIG. 6 is a cross sectional view of a main portionillustrating the surface wiring structure, FIG. 7 is a cross sectionalview of a main portion illustrating the rear face wiring structure (astructure in which bump electrodes are formed to the wiring substrate onthe side of the tape and the elastomer is formed on the side of thewirings) and FIG. 8 is a cross sectional view of a main portionillustrating wirings on both surfaces.

[0156] The package structure of the Embodiment 1 is a so-called “surfacewiring structure” as shown in an enlarged scale in FIG. 6, in which anelastomer 2 is bonded to a flexible wiring substrate 3 on one side of atape 9 (on the side facing the semiconductor chip 1) and a solder resist4 and a bump electrode 5 are formed on the other side of the wirings 10.On the other hand, there is a technique studied by the present inventorwhich may be referred to as a so-called “rear face wiring structure”, asshown in FIG. 7, in which an elastomer 2 is bonded on one side of thewiring 10 and a solder bump 5 is formed on the other side of the tape 9.In FIG. 6, an Au plating 11 a is formed, for example, by an electricfield plating on the surface of a lead 11 on one end and on the surfaceof a land 12 on the other end of the wiring 10.

[0157] In the rear face wiring structure described above with referenceto FIG. 7, a through hole 12 b for joining the bump 5 is formed, forexample, by punching out an opening in the tape 9, which is made of amaterial such as a polyimide resin, whereas in the surface wiringstructure of the Embodiment 1, as seen in FIG. 6, a solder resist 4 madeof a material such as a light sensitive epoxy resin is coated on themain surface of the wiring 10, and a connection hole 12 a of a desiredsize is formed at a desired position by a photographic process, such asexposure and development, so that the following advantages can beexpected.

[0158] (1) Since the opening for the solder bump 5 is formed by exposureand development of the solder resist 4, the fabrication accuracy for thehole diameter can be improved compared with a case of puncturing anopening in the tape 9 of the flexible wiring substrate 3 in the rearface wiring structure by machining.

[0159] (2) While the minimum thickness of the tape 9, in practice, isabout 50 μm, the solder resist 4 can be coated to a thickness of about10 to 20 μm stably depending on the coating condition, so that a smallersolder ball 17 can be joined satisfactorily.

[0160] For example, in a case of forming a solder bump of about 30 μmdiameter, which is less than the thickness of the tape 9, the aspectratio of the through hole is excessively large in the rear face wiringstructure, thereby possibly resulting in a connection failure. On theother hand, the aspect ratio can be lowered to cope with such a problemin the surface wiring structure.

[0161] (3) Since the pitch of the solder bumps 5 can be made smaller inthe surface wiring structure as compared with the rear face wiringstructure, a semiconductor package having output terminals for thesolder bumps arranged with a higher density can be obtained.

[0162] (4) Since an elastomer 2 is disposed on the flat surface at theback of the tape 9, the elastomer 2 can be mounted (coated or appended)in a voidless manner stably with a high accuracy. Further, since thesize and the shape of the elastomer 2 are stabilized, the step ofbonding the semiconductor chip 1 is also stable, thereby making itpossible to conduct assembling at a higher yield.

[0163] As described above, the technique of forming the rear face wiringstructure results in problems, such as in the formation of the openingin the tape 9 of the flexible wiring substrate 3 and in the bondabilitybetween the wirings 10 of the flexible wiring substrate 3 and theelastomer 2, whereas such problems can be solved by adopting the surfacewiring structure as provided in the Embodiment 1.

[0164] Further, in the wiring structure of the flexible wiring substrate3, it is possible to use a flexible wiring substrate 3 having a doubleface wiring structure, for example, as shown in FIG. 8, that is, havinglayered wirings on both surfaces of the tape 9, in addition to thesingle face wiring structure as shown in FIG. 6, and it can be appliedfurther to three or more layered wiring structures.

[0165] In the example of FIG. 8, a first wiring 20 is used as a signalwiring while the second wiring 21 is used as a ground plane, in whichthe second wiring 21 and the bump 5 or the first wiring 20 areelectrically connected by way of a via hole 22. Such a structure has theadvantage of obtaining an excellent electric characteristic, forexample, from the point of view of noise resistance.

[0166] 2. Optimization of tape edge position relative to elastomer

[0167] To assist in providing a technical explanation of theoptimization of tape edge position relative to the elastomer, FIG. 9 isa plane view illustrating window openings, FIG. 10 is a cross sectionalview illustrating a window opening in FIG. 9 and FIG. 11 is a crosssectional view for assisting in the explanation of the size of thewindow opening portion and the edge portion of the semiconductor chip.

[0168] The package structure of the Embodiment 1, as shown in FIG. 9,has a BGA (Ball Grid Array) structure in which the solder bumps 5 arearranged in a matrix on the main surface of the flexible wiringsubstrate 3. In this example, as shown in FIG. 10, the semiconductor 1has a center pad arrangement in which a window opening portion 23 isdisposed longitudinally at a central portion, and the portion and theperipheral edge of the semiconductor chip 1 are resin capsulated by thesealant 6 to attain a structure of high moisture proofness andreliability in the final structure.

[0169] By the way, in the technique studied by the present inventor,when the end of the elastomer 2 (on the side of the window opening 23)is brought closer to the edge of the tape 9, that is, if the length L1between the end of the elastomer 2 of the semiconductor chip 1 on theside of the bonding pad 7 and the end of the tape 9 is reduced,contamination to the lead 11 results due to a bleeding ingredient andvolatile ingredient of the elastomer 2.

[0170] On the other hand, if the length L1 is made larger, that is, ifthe elastomer is excessively retracted from the edge of the tape 9, thelength L2 between the end of the elastomer 2 and the solder bump 5 isreduced, and since the elastomer 2 is not present below the innermostportion of the solder bump 5, this may possibly increase the variationin the height of the solder bump 5 or widen the encapsulation region forthe window opening 23, making it difficult to fill in the sealant 6.

[0171] On the other hand, in the Embodiment 1, these problems can besolved simultaneously by selecting an appropriate length for L1 so as toset the end of the elastomer 2 at an optimal position between the end ofthe tape 9 and the solder bump 5.

[0172] That is, in order to eliminate the foregoing problems related tothe window opening 23, the length L1 is defined as indicated below. Forexample, in this embodiment, the printing accuracy of the elastomer 2 isdefined as about ±100 μm. Accordingly, if the length L1 is less than 100μm, since it may extend outside of the tape 9 due to a printingdeviation, it must be greater than the printing accuracy (100 μm) at theleast.

[0173] Further, since there is no problem from contamination to the lead11 by a bleeding ingredient or volatile ingredient of the elastomer 2 ifit is actually spaced by about 300 μm from the actual edge, the lengthL2 is set, for example, at 300 μm as a minimum. However, a design with aminimum value of about 100 μm is possible if an elastomer 2 of lesscontamination and bleeding is used or a countermeasure, for example,cleaning of the contamination, is adopted.

[0174] As described above, contamination to the lead 11 caused bybleeding ingredients or volatile ingredients of the elastomer 2 can beprevented, the variation in the height of the solder bumps 5 can be madestable and the sealing region of the window opening 23 can be filledwith ease by selecting an appropriate length L1 as provided in theEmbodiment 1.

[0175] 3. Optimization of the outer size of the package

[0176] To assist in providing a technical explanation of theoptimization of the outer size of the package, FIG. 11 is a crosssectional view for explaining the size of the window opening and theedge portion of the semiconductor chip, FIG. 12 is a cross sectionalview illustrating a concave portion of the elastomer after printing andFIG. 13 is a cross sectional view illustrating warp in the tape afterappending a semiconductor chip.

[0177] For example, in the technique studied by the present inventor,looking to FIG. 11 and assuming that the distance between the end of thesemiconductor chip 1 on the outer circumference of the package and theend of the tape 9 of the flexible wiring substrate 3 is M1 and thedistance between the end of the elastomer 2 and the end of the tape 9 isM2, the following problems are present:

[0178] (1) If M1<0, since the outermost circumference of the package isrepresented by the wall of the semiconductor chip 1. there is a greatpossibility of inducing cracks in the semiconductor chip 1 during theassembling step, particularly upon insertion and withdrawal of the chipfrom a receptacle, during tray transportation and the like.

[0179] (2) If M1<0, M2>0, since the circuit surface of the semiconductorchip 1 will be exposed to the outside, a problem may be caused whichaffects the reliability and the sealing for preventing this, althoughthis possibly leads to an increase of the fabrication steps.

[0180] (3) If M1−M2<0, peripheral protrusions of the elastomer 2 afterprinting, as shown in FIG. 12, interferes with the bonding portion ofthe semiconductor chip 1, as shown in FIG. 13, so as to cause bondingfailure upon appending, reducing the flatness of the flexible wiringsubstrate 3 and causing a reduction of the reliability.

[0181] (4) If M2=0, it is necessary to cut the elastomer 2, which causesa problem due to the difficulty of the cutting.

[0182] On the other hand, in the Embodiment 1, the foregoing problemscan be overcome by determining the relationship for the distance betweenthe end of the semiconductor chip 1 or the end of the elastomer 2 andend of the tape 9 as: M1>M2>0. That is, in the explanatory viewillustrating the edge portion of the package in FIG. 11, since thecutting error in the tape cutting step for determining the final outershape is about 100 μm, it is desirable to ensure that M2 is more than100 μm in order that the cutting jig does not reach the elastomer 2.

[0183] By the way, the cross sectional shape after forming the elastomer2 by printing and hardening the same by baking is as shown in FIG. 12,which shows that a peripheral portion tends to be higher as a result ofbeing pulled by the mask upon leaving the plate after printing in a caseof a material having a thixotropic property which is higher to someextent. For example, if the semiconductor chip 1 is appended to theelastomer 2 under the condition that M1<M2 so that the end of thesemiconductor chip extends past the end of the elastomer 2, a problemoccurs in that the surface of the tape 9 warps to conform to the crosssectional shape of the elastomer 2, as shown in FIG. 13.

[0184] In order to prevent this, it is effective to eliminate the highperipheral portion of the elastomer 2 at the outside of thesemiconductor chip 1 by setting M1>M2. For instance, since the width ofthe protrusion is-about 200 μm, it is desirable for (M1−M2.) to be 240μm and the distance M1 to be about 360 μm in view of the distance M2=100μm being provided for the cutting property.

[0185] Cutting the tape 9 at the outer circumference as described aboveprovides advantages in that the outer shape error is reduced, andperipheral jigs such as a receptacle or a tray need not be changed tochange the size to some extent of the semiconductor chip 1.

[0186] As described above, in the Embodiment 1, it is possible to avoidcracking and chipping of the semiconductor chip 1 to improve the cuttingmargin during the cutting step. Further, the circuit surface of thesemiconductor chip 1 can be entirely disposed below the elastomer 2 toprovide the advantage of improving the moisture proofness andeliminating the requirement for sealing the outer circumferentialportion.

[0187] 4. Planer S-shaped lead

[0188] To assist in providing a technical explanation of the planerS-shaped lead, FIG. 14 is a plan view illustrating a planer S-shapedlead, FIG. 15 is a cross sectional view as seen in the direction ofarrow B in FIG. 14, FIG. 16 is a cross sectional view as seen in thedirection of arrow A in FIG. 14, FIG. 17 is a cross sectional viewillustrating the trace of a bonding tool upon forming a standardS-shaped lead and FIG. 18 is a cross sectional view illustrating thetrace of a bonding tool upon forming a planer S-shaped lead.

[0189] The S-shaped configuration is such that the length of a lead 11at one end of a wiring 10 is substantially longer than the lineardistance between a pad 7 of a chip 1 and the edge portion 11 b of thetape 9, so that stresses on the lead 11 can be reduced.

[0190] For example, in the technique of forming a standard S-shaped lead24 as studied by the present inventor, the lead which is employed is alinear notch lead or a beam lead, as shown by the dotted line in FIG.14, and in order to form a sag (S-shaped configuration) sufficient towithstand thermal deformation during bonding, as shown by a fine line inFIG. 15, it is necessary to employ a motion along a special bonding tooltrace 25 which involves first driving down the lead 11 just above thesemiconductor chip 1, then laterally displacing the lead and then againdriving it down onto the bonding pad 7, which operation may require aspecial wire bonder.

[0191] On the other hand, in the Embodiment 1, the foregoing problem canbe solved by preparing the lead 11 of the wiring 10 so that it does nothave a linear shape, but is a planer lead 26 of a S-shaped configurationin which the base portion of the wiring 10 and the bonding portion atthe top end are previously displaced at least by more than the width ofthe lead 11, as shown in FIG. 14, upon forming the wiring 10 on the tape9 of the flexible wiring substrate 3.

[0192] As described above, by such forming of the planer S-shaped lead26, a lead having a stable and suitable S-shaped configuration can beformed by a bonding tool trace 25 by simply driving down a typical wirebonder, as shown in FIG. 18, since a sag due to the original planerS-shaped configuration is formed as shown in FIG. 16, although astraightened shape as shown in FIG. 15 is formed.

[0193] Thus, a planer S-shaped lead 26 of stable S-shaped configurationcan be found with no requirement for a soft-modified special wire bonderand, further, an effect for shortening the contact time upon bonding canalso be expected since the bonding tool trace 25 can also be simplified.

[0194] 5. Beam lead

[0195] To assist in providing a technical explanation of the beam lead,FIG. 19 is a plan view for explaining a notch lead and a beam lead, FIG.20 is a plan view illustrating a notch lead in a portion A of FIG. 19and FIG. 21 is a plan view illustrating a beam lead.

[0196] For example, in the technique studied by the present inventor, asshown in FIG. 20, which is an enlarged view of the lead 11 in FIG. 19,the lead 11 is formed with a notch 27, for example, of a V-shaped cut ata cutting portion. A portion slightly inside of the notch 27 is drivendownwardly by a bonding tool 18 upon bonding, to cut the lead 11 at theportion of the notch 27. However, the width of the notch 27 changes dueto varied etching for the wiring 10 in the manufacturing step forproducing the flexible wiring substrate 3, leading to the possibilitythat the lead will not be cut upon bonding.

[0197] Further, even if it is cut, there still may be a problem in thatthe lead may be cut at a portion different from the desired notch 27, orthe notch may be too narrow resulting in the lead being disconnectedbefore the plating step of the flexible wiring substrate 3, so that theplating can not be accomplished.

[0198] On the other hand, in the Embodiment 1, as shown in FIG. 21, theproblem upon cutting the lead 11 as described above can be overcome byforming the lead with a cantilever beam structure, namely, a so-calledbeam lead 28 in which one end is fixed to the tape 9 of the flexiblewiring substrate 3 and the other end as the cutting side formed with thenotch 27 is left open.

[0199] 6. Passivation size for the periphery of the bonding pad

[0200] To assist in providing a technical explanation of the size of thepassivation film at the periphery of the bonding pad, FIG. 22 is a crosssectional view illustrating a lead bonding portion, FIG. 23 is a planview illustrating a lead bonding portion, FIG. 24 is a cross sectionalview illustrating a tool landing point at the portion in FIG. 22 in anenlarged scale, FIG. 25 is a cross sectional view illustrating a bondingportion improved for the size of the passivation opening and FIG. 26 isa plan view illustrating a bonding portion of a two way lead.

[0201] In a memory chip typically represented by a DRAM or the like, apassivation film 29 made of a polyimide type resin is formed on the chipfor preventing soft errors caused by α-rays.

[0202] For example, in the technique studied by the present inventor,since the lead 11 is first driven downwardly just above thesemiconductor chip 1, then displaced laterally and again drivendownwardly on the bonding pad 7 of the semiconductor chip 1, as shown bythe bonding tool trace 25 in the bonding sequence in FIG. 22, FIG. 23and FIG. 24, there is the possibility of a problem in that thepassivation film 29 on the semiconductor chip 1 or the semiconductorchip 1 therebelow may undergo damage during the first driving downoperation, or ingredients of the passivation film 29 may be deposited tocontaminate the bonding portion on the lower surface of the lead 11 todegrade the bondability.

[0203] On the other hand, in the Embodiment 1, the foregoing problemscan be solved by setting the distance L3 from the edge of the bondingpad 7 to the edge of the passivation film 29 on the side of the bondingpad 7, as seen in FIG. 22, FIG. 23, and FIG. 24, such that thepassivation opening 30 is extended and enlarged, whereby the lead 11does not interfere with the passivation film 29 at least on the sidethereof where the bonding tool 18 is driven down, resulting in animprovement, as shown in FIG. 25.

[0204] That is, in FIG. 24, the size L3 is about 25 Am in an example ofa semiconductor chip 1, for example, a memory device. In this regard,since the size of the bonding pad 7 is 100 μm square and the size of thetop end of the bonding tool 18 is equal to or less than that, thedistance L3 of the passivation film 29 from the pad 7, as seen in FIG.25, is desirably, for example, more than 125 μm.

[0205] As described above, a suitable bonding property can be attainedwithout the risk of damage to the passivation film 29 on thesemiconductor chip 1 or to the semiconductor chip 1 or withoutdeposition of ingredients of the passivation film 29 onto the bondingportion at the lower surface of the lead 11 which could result incontamination.

[0206] Further, in a case where the leads 11 extend in both directions,the problem can also be coped with similarly by enlarging the distancefrom the opening edge of the bonding pad 7 to the edge of thepassivation film 29 on the side of the bonding pad 7 at least on theside where the bonding tool is driven down. Enlargement of the spacebetween the edges causes no problem even if applied to the opposite sideto such an extent as to avoid exposing the circuit surface of thesemiconductor chip 1.

[0207] 7. Improvement of the anchor wiring

[0208] To assist in providing a technical explanation of the improvementof the anchor wiring, FIG. 27 is a plan view illustrating a standardanchor wiring and FIG. 28 is a plan view illustrating an improvedanchor-wiring.

[0209] For example, in the-technique studied by the present inventors,in a pattern of a standard anchor wiring 31 on the terminal end of anotch, as shown in FIG. 27, if the notch 27 is formed to be smaller thana designed value, there is a possibility that the lead will not be cutat the portion of the notch 27, but the bonding strength between thewiring 10 and the tape 9 ahead of the notch in the standard anchorwiring 31 may not be sufficient to prevent a portion of the standardanchor wiring 31 to be peeled from the tape 9.

[0210] On the other hand, in this Embodiment 1, the bonding strengthbetween the wiring 10 and the tape 9 can be increased to obtain a stablecutting performance of the notch 27 by providing an enlarged anchorwiring 32 for enlarging the effective area in the portion for the anchorwiring at the terminal end as shown in FIG. 28.

[0211] That is, the following improved examples of enlarged anchorwirings 32 are shown in FIG. 28.

[0212] (1) An enlarged anchor wiring 32 is connected to a bump land 12to an opposing wiring 11.

[0213] (2) Enlarged anchor wiring 32 is extended longitudinally in avacant space in the wirings 11.

[0214] (3) Enlarged anchor wiring 32 is extended laterally in a vacantspace in the wirings 11.

[0215] (4) Adjacent extended anchor wirings 32 are connected with eachother. In each of the examples, the cutting performance of the notch 27can be stabilized by the increase of the adhesion strength between thewiring 10 and the tape 9 by increasing the effective area of the portionof the enlarged anchor wirings 32.

[0216] 8. Wide elastomer structure

[0217] To assist in providing technical explanation of the wideelastomer structure, FIG. 29 is a perspective vie's illustrating astructure of a standard elastomer, FIG. 30 is a perspective viewillustrating the state of appending a semiconductor chip to a standardelastomer, FIG. 31 is a perspective view illustrating the structure of awide elastomer, FIG. 32 is a perspective view illustrating the state ofappending a semiconductor chip to the wide elastomer and FIG. 33 is across sectional view illustrating the state of appending a semiconductorchip to the wide elastomer.

[0218] In the technique studied by the present inventor, the elastomeris bonded on both sides of a bonding pad 7 of a semiconductor chip 1and, in a structure using a standard elastomer 33, as shown in FIG. 29and FIG. 30, there is a possibility that warping will occur in theflexible wiring substrate due to the effect of peripheral protrusions ina structure in which the surface of the elastomer 2 is smaller than thatof the semiconductor chip 1, as shown in FIG. 13, and that the warpingbrings about a problem, for example, during the forming of the solderbumps 5 and the mounting of the substrate.

[0219] On the other hand, in the structure of a wide elastomer 34 whichis larger than the outer size of the semiconductor chip 1 in theembodiment as shown in FIG. 31, the peripheral protrusions of the wideelastomer 34 are outside of the edges of the semiconductor chip, asshown in FIG. 32 and FIG. 33, after appending the semiconductor chip 1,and since the semiconductor chip 1 is bonded substantially to a flatportion of the wide elastomer 34, warping of the flexible wiringsubstrate 3 can be avoided.

[0220] Further, as shown in FIG. 33, since a wide coating area of anadhesive 8 can be employed, the portion in which the adhesive 8 is notprovided and which is left unbonded is reduced in size, and since theadhesive will extrude uniformly at the periphery of the semiconductorchip 1 to form an adhesive bead 35, it is possible to constitute apackage of excellent moisture proofness and reliability without applyingperipheral sealing.

[0221] More particularly, the width of the protrusions at the peripheryof the wide elastomer 34 is, for example, about 200 to 300 μm dependingon the physical property of the material and, accordingly, the wideelastomer 34 extends over a larger range at the entire circumference atleast by more than the protrusion width afforded by the chip size of thesemiconductor chip 1, as shown in FIG. 33 in the Embodiment 1.

[0222] Further, while the flatness is improved by forming the wideelastomer 34 sufficiently large, if the tape 9 is to be cut just at theouter circumference of the semiconductor chip 1, the tape 9 will be cuttogether with the wide elastomer 34 along a cutting line 36, which isnecessary to define the package outer shape.

[0223] As described above, by using the wide elastomer 34 which islarger than the outer size of the semiconductor chip 1, warping of theflexible wiring substrate 3 can be suppressed, and the bondability ofthe semiconductor chip 1 can be made stable to improve the moistureproofness and the reliability of the package.

[0224] 9. Groove-filling technique of the elastomer

[0225] To assist in providing a technical explanation of thegroove-filling technique of the elastomer, FIG. 31 and FIG. 32 areperspective views illustrating the structure of the wide elastomer andthe state of appending the semiconductor chip as described above, FIG.34 is a perspective view illustrating the structure after appending asemiconductor chip to a standard elastomer, FIG. 35 is a cross sectionalview thereof, FIG. 36 is a perspective view illustrating a structureafter appending a semiconductor chip to a wide elastomer, FIG. 37 is across sectional view thereof, FIG. 38 is a cross sectional viewillustrating the concept of metal mask printing, FIG. 39 is a plan viewillustrating a metal mask of a standard elastomer, FIG. 40 is a planview illustrating a metal mask of a wide elastomer, FIG. 41 is a planview illustrating a printed shape of an wide elastomer having pluralbridge portions and FIG. 42 is a plan view illustrating a pottingposition for groove-filling of the wide elastomer.

[0226] For example, in the structure of a standard elastomer 33 as shownin FIG. 34 and FIG. 35, in the technique studied by the presentinventor, when an elastomer is formed by printing using a metal mask 37,as shown in FIG. 39, in the structure of the standard elastomer 33 shownin FIG. 34 and FIG. 35, since a bridge portion 39 is always presentacross the printing area opening 38 of the metal mask 37 shown in FIG.39, a groove 40 (space) surrounded by walls of the semiconductor chip 1and the elastomer is present below the tape suspended portion.

[0227] Accordingly, when the window opening 23 (FIG. 9) isresin-encapsulated in a structure in which the groove 40 remains at theends of the space defined by the semiconductor chip 1 and the elastomer,the sealant 6 will leak through the groove 40, and so it is necessary topreviously seal the open end portions by a method such as separatepotting and then seal the window opening 23.

[0228] As described above, the concept of printing by use of a metalmask 37 is designed to form the elastomer for a desired range to adesired thickness, by positioning and disposing a metal mask 37 having aprinting area opening 38 at a predetermined position with respect to aflexible wiring substrate 3, only for the printed portion as shown inFIG. 39 in the case of the standard elastomer 33 and as shown in FIG. 40in the case of the wide elastomer 34.

[0229] Accordingly, in the Embodiment 1, the wide elastomer 34 describedabove and shown in FIG. 31 is printed by a metal mask 37 as shown inFIG. 40, in which a groove 40 surrounded by the walls of thesemiconductor chip 1 and the elastomer 2 can be narrowed by printing theelastomer having a restricted bridge portion 39 for the printing areaopening 38 of the metal mask 37. For example, the minimum value for thewidth of the groove 40 determined by the strength of the bridge portion39 of the metal mask 37 is about 200 μm.

[0230] Further, in a case of a structure in which the semiconductor chipis appended to the elastomer by coating the adhesive 8 on the mainsurface of the elastomer 2, if the adhesive 8 is coated in a sufficientamount, excessive adhesive 8 will fill the groove 40 in response to thepressure created upon appending to make the window opening 23 a closedspace, so that the window opening 23 can be sealed without applyingsealing.

[0231] Further, the groove-fillage can be improved by restricting thebridge portion 39 of the metal mask 37 thereby narrowing the groove 40,but this results in a side effect of lowering the strength of the metalmask 37. However, by providing a plurality of bridge positions on oneside to produce the construction as shown in FIG. 41, the strength ofthe metal mask 37 can be improved without changing the width of thegroove 40 although the number of the grooves 40 is increased.

[0232] Further, with an aim toward improving the groove-fillage, asshown in FIG. 42, when resin, adhesive or the like is potted, forexample, at the potting position 42 of the groove 40 of the elastomer toform a stopping dam for the sealant flow just before appending thesemiconductor chip 1 the groove-fillage can be improved still further.

[0233] Further, in a case of filling by potting before sealing thewindow opening 23 after appending and bonding of the semiconductor chipas in the technique studied above, the sealing performance can beimproved outstandingly by restricting the width of the groove 40.

[0234] As described above, the groove-fillage can be improved,particularly, by restricting the bridge portion 39 of the metal mask 37thereby narrowing the groove 40 of the elastomer and, further, thegroove-fillage can be improved even more by previously forming astopping dam for the sealant flow to the potting position 42.

[0235] 10. Inner lead bonding technique

[0236] To assist in providing an explanation of the inner lead bondingtechnique, FIG. 43 is a cross sectional view illustrating a bondingportion produced by a standard lead bonding, FIG. 44 is a crosssectional view illustrating a bonding portion produced by using a studbump, FIG. 45 and FIG. 46 are a cross sectional view and a plan view,respectively, illustrating a lead connection using soldering, FIG. 47and FIG. 48 are a cross sectional view and a perspective view,respectively, illustrating a lead connection using a solder or Au ball,FIG. 49 is a cross sectional view illustrating a connection using an Alor solder wire and FIG. 50 is a cross sectional view illustrating aconnection using an Au wire.

[0237] For example, in the technique studied by the present inventor, alead 11 on which Au plating is provided is directly driven onto abonding pad 7 and thermally press bonded using supersonic waves. In thiscase, if the bonding condition is poor or the shape of the bonding tool18 is inadequate, there is the possibility of a problem in that thebonding strength is low or the bonding pad for a portion therebelow issubject to damage.

[0238] On the contrary, in the Embodiment 1, the problems, for example,of bondability or damage caused by the bonding condition and the shapeof the bonding tool 18 as described above can be overcome by adoptingthe following feature for the bonding state.

[0239] That is, FIG. 44 shows an example of using a stud bump 43. Thisexample has a feature of using a semiconductor chip 1 having the studbump 43 formed previously by a plating method or a ball bonding methodonto a bonding pad 7 of the semiconductor chip 1, causing thebondability to be improved and, further, preventing damage to thebonding pad.

[0240] Further, FIG. 45 and FIG. 46 are examples of a connection for thelead 11 using solder and showing a connection state in which the lead 11is surrounded with solder 44. This example concerns a technique forconnecting a bonding pad 7 comprising Al or the like of thesemiconductor chip 1 and an electrode of the tape 9 such as TAB as a CSPsubstrate. A method of feeding the solder in this example includes amethod of connecting the solder 44 with the bonding pad 7 of thesemiconductor chip 1 using the tape 9 on which the solder 44 is alreadypresent so as to surround the lead 11.

[0241] For the connection method, it is desirable for the shape of thesolder 44 provided on the tape 9, such as a TAB, to be made as flat aspossible at the surface in contact with the bonding pad 7 of thesemiconductor chip 1 in the connection method by pressurizing andheating using a bonder. Further, in a connection method using a reflowfurnace, solder paste or flux is provided at the surface of the bondingpad 7 of the semiconductor chip 1 so as to be in contact with the solder44 of the tape 9, such as a TAB.

[0242] Then, in the case of feeding the solder 44 using solder paste,the solder paste may be provided at the surface of the bonding pad 7 ofthe semiconductor chip 1 by printing or by using a syringe. In thiscase, the tape 9, such as a TAB, may be bonded previously orsubsequently providing that the lead 11 of the tape 9 is in contact withthe solder 44 when the tape 9 is bonded to the semiconductor chip 1.

[0243] Further, FIG. 47, FIG. 48 show a connection technique having afeature of connecting a lead 11 of a tape 9, such as a TAB, onto abonding pad 7 of a semiconductor chip 1 by using a stud bump, such as asolder or Au ball 45.

[0244] Further, FIG. 49 shows an example of connecting a wiring 10 of aflexible wiring substrate 3 and a bonding pad 7 of a semiconductor chip1 by using an Al or solder wire 46. Further, FIG. 50 shows an example ofconnecting a wiring 10 of a flexible wiring substrate 3 and a bondingpad 7 of a semiconductor chip 1 by using an Au wire 47. In theconnection examples, the connection is enabled not by way of the innerlead bonding, such as a TAB, but under the concept of a typical wirebonding.

[0245] 11. Lead design technique capable of forming an S-shape with notool return

[0246] To assist in providing an explanation of the lead designtechnique capable of forming an S-shape with no tool return, FIG. 17 isa cross sectional view illustrating a trace of a bonding tool uponforming a standard S-shaped lead as explained previously, FIG. 51 is aperspective view for explaining the lead design, FIG. 52 is aperspective view illustrating deformation of a lead after bonding, FIG.53 is a chart illustrating a relationship between a lead size and abending stress ratio and FIG. 76 to FIG. SO are cross sectional viewsillustrating the deformed shape of a lead in accordance with the bendingstress ratio.

[0247] More particularly, as explained also in connection with thetechnique for the planer S-shaped lead 26 in the technique studied bythe present inventor, it is necessary for forming the S-shapedconfiguration of the lead 11 shown in FIG. 17, to laterally displace thebonding tool 18, namely, a special bonding tool trace 25 including atool return is required.

[0248] On the contrary, in the Embodiment 1, if the size of a lead 11shown in FIG. 51 is defined, for example, as shown in FIG. 53, thebending stress ratio a will fall within a desired range of from 1.2 to1.5 and a suitable S-shaped configuration for the lead 11 as shown inFIG. 52 can be formed by merely driving down the bonding tool 18vertically with no tool return. In FIG. 52, there are shown a tape end48, an end 49 on the side of the tape and an end 50 on the side of thechip.

[0249] For example, in the example of embodiment (1), the bending stressratio α=1.26 at the size: taper length L1=100 μAm, wiring length L2=380μm, taper width b1=65 μm, lead width b2=38 μm and lead thickness h=18μm. In the same manner, the ratio is 1.25 in the embodiment (2), 1.26 inthe embodiment (3), 1.31 in the embodiment (4) and 1.46 in theembodiment (5).

[0250] On the contrary, in the studied technique, at the size: taperlength L1=100 μm, wiring length L2=280 μm, taper width b1=60 μm, leadwidth b2=38 μm and lead thickness h=18 μm, the bending stress ratio α is1.02, for example, in the example (1) and 1.13 in the example (2) whichis out of the range of 1.2 to 1.5.

[0251] As described above, since the bending stress is concentrated toan intermediate portion of the lead 11 in the wiring operation withinthe range of the bending stress ratio a from 1.2 to 1.5, a moderatelydistorted satisfactory wiring state is attained. On the other hand, ifthe bending stress ratio a is less than 1.2 as in the studied technique,since the bending stress is concentrated at the tape end 48 of the lead11, it results in a stiffened state. Further, if the ratio exceeds 1.5,the bending stress is concentrated only at the intermediate portion ofthe lead 11 resulting in a state of a small radius of curvature whichcan not be said to be a satisfactory wiring state.

[0252]FIG. 76 to FIG. 80 show the deformed shape of the lead inaccordance with the bending stress ratio a concretely. At first, whenthe bonding tool 18 is merely driven down vertically to contact the leadof initial shape before wiring shown in FIG. 76, since the bendingstress is concentrated on the tape end 48 of the lead 11, for example,in the wiring operation at α<0.9, an extremely stiffened wiring state isformed as shown in FIG. 77. Accordingly, since high repeating stressesare exerted on the lead 11 during the temperature cycle after wiring,the fatigue life is extremely shortened.

[0253] Further, since the bending stress is concentrated at the tape end48 of the lead 11 in the wiring operation at 0.9≦α≦1.2 as in thetechnique studied by the present inventor, a somewhat stiffened wiringstate is formed as shown in FIG. 78. Accordingly, since high repeatingstresses are exerted on the lead 11 during the temperature cycle afterthe wiring, fatigue life is shortened.

[0254] On the contrary, since the bending stress is concentrated at anintermediate portion of the lead 11 during the wiring operation at1.2≦α<1.5 as in the Embodiment 1, a moderately distorted wiring state asshown in FIG. 79 is formed. Accordingly, since no high repeatingstresses are exerted on the lead 11 during the temperature cycle afterthe wiring, the fatigue life is increased.

[0255] Further, during wiring operation at 1.5<α with an increasedbending stress ratio, since the bending ratio is concentrated only atthe intermediate portion of the lead 11, a wiring state with a smallradius of curvature as shown in FIG. 80 is formed. Accordingly, sincethe initial strength of the bent portion is lowered, the fatigue lifeduring the temperature cycle after wiring is shortened.

[0256] As a result, an optimal wiring state with only a moderatelydistorted wiring shape is formed when the bending stress ratio is setwithin a range: 1.2≦α≦1.5 as in the Embodiment 1, and the temperaturecycle life of the lead 11 can be increased.

[0257] The bending stress ratio α is defined as a value formed bydividing the stress σ1 generated at the end 49 of the lead 11 on theside of the tape by a stress σ0 generated at the tape end 48 of the lead11 upon conducting the operation of raising the lead 11 just above thebonding pad 7 with the bonding tool 18. That is, the bending stressratio α can be represented by the following formula based on the size ofthe lead 11 having a feature in the tapered shape:

α=σ1/σ0=b1×(L2−L1)/(b2×L2)

[0258] As described above, when the size and the shape of the lead 11are designed such that the bending stress ratio α is from 1.2 to 1.5, astable and suitable S-shaped wiring state can be formed by a simpledriving down movement of a wire bonder like that in the technique forthe planer S-shaped lead 26 described previously. Accordingly, since nospecial soft-modified wire bonder is required and the bonding tool trace25 can also be simplified, an effect of shortening the contact time uponbonding can also be expected.

[0259] 12. Ni-platingless lead

[0260] To assist in providing a technical explanation of theNi-platingless lead, FIG. 54 is a cross sectional view illustrating aconnection portion of the lead, FIG. 55 is an enlarged cross sectionalview illustrating a bent portion of a lead, FIG. 56 is an enlarged crosssectional view illustrating a bent portion of an Ni-platingless lead,FIG. 57 is an enlarged cross sectional view illustrating a press contactportion of a lead and FIG. 58 is an enlarged cross sectional viewillustrating a press-contact portion of the Ni-platingless lead.

[0261] As an example, in the technique studied by the present inventor,in the case of a cross sectional structure of a lead 11 in whichNi-plating is applied to a surface of a Cu core and an Au plating isapplied thereon, wherein a Cu core lead is employed instead of a pure Aulead, since the Ni-plating layer is hard and brittle, if it is intendedto produce an S-shaped lead configuration, there is the possibility ofcausing a crack 51 to occur at the bent portion of the lead 11 as shownin FIG. 55, or the bonding pad 7 or a portion therebelow may besubjected to damage 52 as shown in FIG. 57. The Ni-plating is formed asa barrier layer for preventing Cu atoms from diffusing to the Au platingsurface.

[0262] On the contrary, in the Embodiment 1, since both the hardness andthe brittleness are reduced by using an Ni-platingless lead 11 in orderto obtain the S-shaped configuration, the crack 51 is less likely toform the lead per se and, in addition, the damage 52 to thesemiconductor chip 1 at the counter-bonding face can also be moderated.

[0263] That is, in the connection state of the lead 11 as shown in FIG.54, in the lead having the constitution of a Cu core 53+Ni plating 54+Auplating 55, as shown in FIG. 55 as an enlargement of the portion A inFIG. 54, the crack 51 is liable to be caused as the radius of curvaturein the bent portion is smaller. On the other hand, if the surface of thelead 11 is free from the Ni plating 54 and, for example, is formed onlywith the Au plating 55 as shown in FIG. 56, the crack 51 is less likelyto form at the bent portion of the lead 11 even if the radius ofcurvature is identical with that in FIG. 55.

[0264] Further, also in a press-contact portion of the lead 11 in FIG.57, illustrating an enlargement of the portion B in FIG. 54, the lead 11has a constitution comprising: cu core 53+Ni plating 54+Au plating 55,and so damage 52 is liable to be caused at the periphery of a bondingpad 7. On the other hand, if the surface of the lead 11 is free from theNi plating 54 and, for example, is formed only with the Au plating 55 asshown in FIG. 58, the damage 52 is less likely even in a case of bondingunder the same lead bonding condition.

[0265] As described above, it is possible to suppress the occurrence ofa crack 51 in the lead 11 and moderate the damage 52 to thesemiconductor chip 1 while obtaining the S-shaped configuration, byconstituting the lead 11 such that only one plating layer, for example,an Au plating is formed on the core material of the Cu core 53.

[0266] Therefore, according to the semiconductor integrated circuitdevice in the Embodiment 1, excellent effects can be obtained as alreadyexplained by comparison with the package structure studied by thepresent inventor, in the CSP package technique of substantially theidentical size with that of the semiconductor chip, in each of thetechnical items, namely: 1. Surface wiring structure, 2. Optimization ofthe tape edge position relative to the elastomer, 3. Optimization ofouter size of the package, 4. Planer S-shaped lead, 5. Beam lead, 6.Peripheral PIQ size of bonding pad, 7. Improvement of anchor wiring, 8.Wide elastomer structure, 9. Elastomer groove-fillage technique, 10.Inner lead bonding technique, 11. Lead design technique capable offorming S-shaped configuration with no tool return and 12.NI-platingless lead.

[0267] In the Embodiment 1, although various explanations have been madewith reference to the drawings and the contents of various techniques onthe premise of a particular surface wiring structure, the technicalitems 2 to 12 are not limited to the described surface wiring structure,but the technique of this invention is applicable also to generalpackage structures, such as a rear face wiring structure. Accordingly,it can be expected that the same effect as explained with reference toall of the items can be obtained when the invention is applied to ageneral package structure.

[0268] The package structure of the Embodiment 1 (FIG. 1, FIG. 2) isshown for a case in which the elastomer 2 is larger than the outer shapeof the semiconductor chip 1. In a case where the elastomer 2 is smallerthan the outer shape of the semiconductor chip 1, as shown in FIG. 81,an improvement of the moisture proofness or the like can be obtained byforming a package structure in which the lateral sides of thesemiconductor chip 1 and the elastomer 2 are covered with a sealant 6.

Embodiment 2

[0269]FIG. 59 and FIG. 60 are a cross sectional view and a perspectiveview, respectively, illustrating a rear face wiring solder resiststructure in the semiconductor integrated circuit device of Embodiment 2according to the present invention.

[0270] The semiconductor integrated circuit device of the Embodiment 2is a ball grid array type semiconductor package like that of theEmbodiment 1, but it is different from the Embodiment 1 in that it isnot based on the surface wiring technique, but is based on and providedfor improving a rear face wiring structure. For instance, as shown inFIG. 59 and FIG. 60, in a structure comprising an elastomer 2 (elasticstructural material) bonded on a main surface of a semiconductor chip(not shown) and a flexible wiring substrate 3 (wiring substrate) bondedto a main surface of the elastomer 2, a solder resist 56 (insulationfilm) is formed on the rear face of the flexible wiring substrate 3.

[0271] That is, the flexible wiring substrate 3 comprises a tape 9(substrate base material) serving as a base material for the flexiblewiring substrate 3 and wirings 10 bonded to the rear face of the tape 9,in which the rear face of the wiring 10 is bonded by way of the solderresist 56 to the elastomer 2. The solder resist 56 is composed of aninsulation material, such as a light sensitive epoxy resin like that inthe Embodiment 1.

[0272] The feature of the package structure of the semiconductorintegrated circuit device in the Embodiment 2 will be explained,including the structure and the process of manufacture in comparisonwith a package structure employing a technique studied by the presentinventor.

[0273] For instance, in the rear face wiring structure shown in FIG. 7,in the Embodiment 1 as the technique studied by the present inventor,since the elastomer 2 is formed directly on the main surface of thewirings 10 of the flexible wiring substrate 3, low molecular weightingredients of the elastomer 3 bleed directly to the lead 11 and if theybleed as far as the bonding point of the lead 11, there is a likelihoodof extremely deteriorating the bondability (wire bonding stress) due tothe contamination.

[0274] Further, compared with the direct plating surface of the lead 11,the surface of the tape 9 in which the wirings 10 are etched out betweenthe leads 11 suffers from violent bleeding since the surface of the tape9 is roughened also with an aim of improving the bondability between thetape 9 and the wirings 10, and bleeding tends to be most violent at theedge portion of the lead 1 together with the effect of the surfacetension.

[0275] Further, in the rear face wiring structure in which the elastomer2 is formed on an uneven surface of the wirings 10 caused by differentlevels between the portions with or without the wirings 10, voids areliable to be left, for example, in the gap between the wirings, whichmay cause a degrading of the reliability.

[0276] On the contrary, in the Embodiment 2, since the solder resist 56is formed on the wirings 10 after forming the wirings 10 in themanufacturing step for the flexible wiring substrate 3, direct contactof the elastomer 2 with the wirings 10 can be prevented. In the samemanner, contact of the elastomer 2 to the roughened surface of the tape9 can also be prevented. This can suppress bleeding of the low molecularweight ingredients of the elastomer 2.

[0277] Further, by coating the solder resist 56 on the uneven surface ofthe wirings 10 of the flexible wiring substrate. the surface of thewirings 10 is flattened to avoid a disadvantage, such as the creation ofvoids upon forming the elastomer 2.

[0278] Accordingly, in the semiconductor integrated circuit device ofthe Embodiment 2, since the solder resist 56 is formed on the wirings 10of the flexible wiring substrate 3 in the CSP semiconductor packagetechnique based on the rear face wiring structure, it is possible toprevent the lowering of the bondability while preventing contaminationto the lead 11, thereby providing a package structure of highreliability with no voids.

Embodiment 3

[0279]FIG. 61 is a plan view of a semiconductor integrated circuitdevice forming an Embodiment 3 according to the present invention, asviewed from the rear face of a semiconductor chip, FIG. 62 is a planview thereof, FIG. 63 is a cross sectional view thereof, FIG. 63 is anenlarged cross sectional view of a portion A in FIG. 63 and FIG. 65 is aplan view for explaining the wiring structure of the wiring substrate.

[0280] A semiconductor integrated circuit device in the Embodiment 3adopts, instead of a semiconductor package having a structure in whichthe bonding pad is formed approximately at the center of the chip, as inthe Embodiments 1 and 2 described above, a packaging structure using asemiconductor chip 1 a in which a pad is formed to the periphery of thechip, as shown in FIG. 61 to FIG. 65, and in which bumps 5 a connectedto the bonding pads to the semiconductor chip 1 a are disposed in aregion inward of the outer circumference of the semiconductor chip 1 a.The Embodiment 3 also has a structure which adopts the techniques from“1. Surface wiring structure” to “12. Ni-platingless lead” of Embodiment1, as well as the technical features of each of the technical items forthe rear face wiring solder resist structure as explained with referenceto the Embodiment 2.

[0281] That is, the semiconductor integrated circuit device in theEmbodiment 3 is, for example, a 24 pin ball grid array typesemiconductor package structure, in which an elastomer 2 a (elasticstructural material), a flexible wiring substrate 3 a (wiring substrate)having wirings 10 a formed on a tape 9 a and a solder resist 4 a(insulation film) are disposed on a main surface of a semiconductor chip1 a formed with a plurality of bonding pads 7 a (external terminals),solder bumps 5 a (bump electrodes) are formed to an opening of thesolder resist 4 a, and a portion for forming the bonding pads 7 a andlateral sides of the elastomer 2 a and the flexible wiring substrate 3 aare covered with a sealant 6 a.

[0282] The semiconductor chip 1 a has a peripheral pad structure, forexample, as shown in FIG. 65, in which a plurality of bonding pads 7 aare arranged in a square pattern along the outer circumference of thesemiconductor chip 1 a. Each bonding pad 7 a of the semiconductor chip 1a is connected electrically with a solder bump 5 a by way of the wiringboa of the flexible wiring substrate 3 a, which is connected at one endof the lead 11 a to the pad 7 a and joined at the bump land 12 a at theother end of the wiring b1 a to the bump 5 a. The solder bumps 5 a arearranged as a 6 row×4 column matrix in a region inward of thearrangement for the bonding pads 7 a.

[0283] Accordingly, in the semiconductor integrated circuit device ofthe Embodiment 3, excellent effects can be obtained for each of thetechnical items as explained for the Embodiments 1 and 2, although thereis a difference in the semiconductor package structure relating to thefan-in peripheral pads. Particularly, in the fan-in package structure, aCSP structure package about the same size as the semiconductor chin 1 acan be attained similar to that in the Embodiments 1 and 2.

Embodiment 4

[0284]FIG. 66 is a plan view of a semiconductor integrated circuitdevice forming an Embodiment 4 of the present invention as viewed fromthe rear face of the semiconductor chip, FIG. 67 is a plan view thereof,FIG. 68 is a cross sectional view thereof, FIG. 69 is an enlarged crosssectional view illustrating a portion A in FIG. 68 and FIG. 70 is a planview for explaining the wiring structure of a wiring substrate.

[0285] The semiconductor integrated circuit device of the Embodiment 4adopts, instead of a semiconductor package having a structure in whichthe bump electrodes are disposed in the chip area as in the Embodiments1 and 2, a package structure using a semiconductor chip 1 b of aperipheral pad structure as shown in FIG. 66 to FIG. 70, in which bumps5 b connected to the bonding pads of the semiconductor chip 1 b aredisposed to a region outward of the outer circumference of thesemiconductor chip 1 b. This Embodiment 4 also has a structure foradopting the technique from “1. Surface wiring structure” to “1-2.Ni-platingless lead”, as explained for the Embodiment 1, as well as thefeatures for each of the technical items of the rear face wiring solderresist structure explained for the Embodiment 2, respectively.

[0286] That is, the semiconductor integrated circuit device of theEmbodiment 4 has, for example, a 80 pin ball grid array typesemiconductor type package structure in which an elastomer 2 b (elasticstructural material), a flexible wiring substrate 3 b (wiring substrate)having wirings 10 b formed on a tape 9 b, and a solder resist 4 b(insulation film) are disposed on a main surface of a semiconductor chip1 b formed with a plurality of bonding pads 7 b (external terminals),solder bumps 5 b (bump electrodes) are formed to an opening portion ofthe solder resist 4 b, portions for forming bonding pads 7 b are coveredwith the sealant 6 b, and a support ring 57 b is disposed to the lateralside of the semiconductor chip 1 b to constitute a package structure.

[0287] The semiconductor chip 1 b has a peripheral pad structure, forexample, as shown in FIG. 70, and a plurality of bonding pads 7 b arearranged in a square pattern along the outer circumference of thesemiconductor chip 1 b. Each bonding pad 7 b of the semiconductor chip 1b is connected electrically with a solder bump 5 b by way of the wiringlob of the flexible wiring substrate 3 b, which is connected at one endof the lead l1 b with the pad 7 b and joined at the bump land 12 b atthe other end with the bump 5 b. The solder bumps 5 b are arranged intwo rows in a square pattern concentric to the arrangement of thebonding pads 7 b of the semiconductor chip 1 b.

[0288] Accordingly, the semiconductor integrated circuit device of theembodiment 4 can also provide excellent effects for each of thetechnical items as explained for the Embodiments 1 and 2, althoughhaving a different semiconductor package structure of fan-out peripheralpad configuration. Particularly, the fan-out package structure canprovide a package structure corresponding to multi-pin arrangements,although the size of the semiconductor package is increased comparedwith the Embodiments 1 and 2.

Embodiment 5

[0289]FIG. 71 is a plan view of a semiconductor integrated circuitdevice forming an Embodiment 5 of the present invention as viewed fromthe rear face of the semiconductor chip, FIG. 72 is a plan view thereof,FIG. 73 is a cross sectional view thereof, FIG. 74 is an enlarged crosssectional view illustrating a portion A in FIG. 73 and FIG. 75 is a planview for explaining the wiring structure of a wiring substrate. In FIG.75, a portion, such as a number of the bonding pads and solder bumps, isomitted for simplification in order to make the arrangement of thewirings clearer.

[0290] The semiconductor integrated circuit device of the Embodiment 5adopts, instead of a semiconductor package having a structure in whichbump electrodes are disposed in the area of the chip as in theEmbodiments 1 and 2, a package structure using a peripheral padstructure semiconductor chip 1 c as shown in FIG. 71 to FIG. 75, inwhich solder bumps 5 c connected to the bonding pads of thesemiconductor chip 1 c are disposed both in inner and outer regions ofthe semiconductor chip 1 c. This Embodiment 5 also has a structureadopting the technique from “1. Surface wiring” to “12. Ni-platinglesslead” as explained for the Embodiment 1, as well as features for each ofthe technical items of the rear face wiring solder resist structure, asexplained for the Embodiment 2.

[0291] That is, the semiconductor integrated circuit device in theEmbodiment 5 is, for example, a 110 pin ball grid array typesemiconductor package structure in which an elastomer 2 c (elasticstructural material), a flexible wiring substrate 3 c (wiring substrate)having wirings 10 c formed on a tape 9 c, and a solder resist 4 c(insulation film) on a main surface of a semiconductor chip 1 c formedwith a plurality of bonding pads 7 c (external terminals), solder bumps5 c (bump electrodes) are formed to an opening portion of the solderresist 4 c, a portion of forming the bonding pads 7 c is covered with asealant 6 c and a support ring 57 c is disposed to the lateral sides ofthe semiconductor chip 1 c.

[0292] The semiconductor chip 1 c has a peripheral pad structure, forexample, as shown in FIG. 75 (actual arrangement in FIG. 72) in which aplurality of bonding pads 7 c are arranged in a square pattern along theouter circumference of the semiconductor chip 1 c. Each bonding pad 7 cof the semiconductor chip 1 c is electrically connected to a solder bump5 c by way of the wiring 10 c of the flexible wiring substrate 3 c thatis connected by a lead 11 c at one end to the pad 7 c and joined to thebump 5 c at the bump land 12 c at the other end of the wiring 10 c. Thesolder bumps 5 c are arranged as 6 row×5 column array in a region inwardof the arrangement of the bonding pads 7 c of the semiconductor chip 1c, and is arranged in two rows in a square pattern also in the outerregion.

[0293] Accordingly, the semiconductor integrated circuit device of theEmbodiment 5 can also obtain the same excellent effect in each of thetechnical items as explained for the Embodiments 1 and 2, although thereis a difference in the semiconductor package structure. Particularly, inthe fan-in/out package structure, a package structure capable of copingwith multi-pin arrangements can be adopted, although the size of thesemiconductor package is enlarged compared with the Embodiments 1 and 2.

[0294] While the invention made by the present inventor has beenexplained with reference to the Embodiments 1-5 of the invention, thepresent invention is not restricted only to those embodiments, but itwill be apparent that various modifications are possible within a rangenot departing from the gist thereof.

[0295] For example, the techniques in the Embodiments 1-5 can becombined as required.

[0296] The number of the solder bumps serving as external connectionterminals of the semiconductor package and the bonding pads serving asexternal terminals of the semiconductor chip electrically connected withthe solder bumps are not restricted only to those described inconnection with the embodiments, but they may be properly modifieddepending on or in accordance with the specification of the packages,such as the integrated circuits formed on the semiconductor chip.

[0297] Further, regarding the materials, for example, for the elastomerforming the elastic structural material, the tape for the flexiblewiring substrate, the wiring and lead plating, the solder resist servingas the insulation film and the solder bump serving as a bump electrode,the invention is also applicable in a case of using other materialshaving respective properties.

[0298] For example, as the solder resist, there can be mentioned a resinmixture comprising an acrylic resin and an epoxy resin, the resinmixture described above with addition of a filler, melamine, acryl,polystyrol and polyimide, as well as polyurethane and silicone;although, it is necessary that they have a property of withstanding thesoldering temperature and have a resistance to the exposure of a fluxand a cleaning solvent.

[0299] Advantageous effects obtained by typical examples among thosedisclosed in accordance with the present invention are briefly explainedbelow.

[0300] (1) Since the elastic structural material is disposed on the flatsurface on the rear face of the substrate base material by adopting asurface wiring structure in which the elastic structural material isdisposed on the rear face of the substrate base material of the wiringsubstrate, and the insulation film is formed on the main surface of thewirings formed on the main surface of the substrate base material, theelastic structural material can be mounted with a higher accuracy andstably to the substrate base material in a voidless manner and, sincethe size and the shape of the elastic structural material are madestable, the bonding step for the semiconductor chip is also stable,thereby enabling assembling at a higher yield.

[0301] (2) Since the signal wiring layer and the power source groundwiring layer can be separated into different layers by making thewirings of the wiring substrate into a multi-wiring layer structure, anexcellent electric characteristic in view of noise resistance can beattained.

[0302] (3) Since external terminals of the semiconductor chip can bedisposed at the central portion or the peripheral portion, and the bumpelectrodes connected to the external terminals can be disposed to theinside, outside or both of the regions outward of the outercircumference of the semiconductor chip, the invention is applicable topackage structures of various types and variations.

[0303] (4) Since the edge position of the substrate base material can beoptimized relative to the elastic structural material by setting thedistance between the end of the elastic structural material of thesemiconductor chip on the side of the external terminals and the end ofthe substrate base material of the wirings substrate based on theingredients of the elastic structural material, a variation in theheight of the bump electrodes is not caused, thereby avoiding anydifficulty in filling the sealant caused by an enlarged sealing regionfor the opening of the elastic structural material and it is possible toprevent contamination of wirings caused by the bleeding of ingredientsor evaporative ingredients of the elastic structural material.

[0304] (5) Since the outer size of the package can be optimized bysetting the relation for the distance M2 between the end of thesubstrate base material of the wiring substrate and the end of theelastic structural material and for the distance M1 between the end ofthe semiconductor chip and the end of the substrate base material at theouter circumference of the semiconductor integrated circuit devicewithin a range: M1>M2>0. the outermost circumference of the package isnot formed by the semiconductor chip, so that a possibility of inducingchip cracks is reduced during the assembling step, as well as duringwithdrawal and insertion of receptacles and tray transportation, and thecircuit surface of the semiconductor chip is not exposed to the outside,thereby making it possible to improve the reliability. Further, sincethe peripheral protrusions of the elastic structural material afterprinting do not interfere with the bonding portion of the semiconductorchip, it is possible to prevent bonding failure upon appending the chip,worsening of the flatness of the wiring substrate and lowering of thereliability.

[0305] (6) Since the planer S-shaped wiring can be obtained by formingthe wiring of the wiring substrate such that the fixed portion with thesubstrate base material and top end portion connected to the externalterminal of the semiconductor chip are displaced at least by more thanthe width of the wiring, a stable and suitable S-shaped lead can beformed because a sag due to the original planer S-shaped configurationcan be obtained by a simple driving down movement of a typical wirebonder, so that a stable S-shaped configuration can be formed for thelead with no requirement of a soft-modified special wire bonder, andfurther, the contact time upon bonding can also be shortened since thebonding tool trace can also be simplified.

[0306] (7) Since the beam wiring can be attained by forming the wiringof the wiring substrate as a cantilever structure which is fixed at oneend to the substrate base material, it is possible to overcome suchproblems as occur in notched wirings wherein cutting is often impossibleduring bonding due to the variation of the size of the notches and, evenif the wiring can be cut, it may be cut at a portion different from thedesired notch, or it may be cut before the plating step for the wiringsubstrate because of the excessively narrowed portion, thereby failingto deposit plating.

[0307] (8) Since the end of the opening of the surface protection filmon the semiconductor chip is set to a size within a range wherein thewiring does not interfere with the surface protection film when thebonding tool is driven down, it is possible to overcome the problem thatthe surface protection film or the semiconductor chip suffers fromdamages (on the semiconductor chip) by the driving down pressure of thetool, and the ingredients of the surface protection film are preventedfrom being deposited on the bonding portion at the lower surface of thelead to cause contamination and to worsen the bondability.

[0308] (9) since the effective area of the wired portion can be enlargedby connecting the wiring on the notch terminal end of the wiringsubstrate to an opposing land portion of the wiring, longitudinally orlaterally extending the wiring in the vacant regions of the wirings orconnecting the adjacent wirings to each other, it is possible toincrease the bonding strength between the wiring and the substrate basematerial and obtain a stable notch cutting performance.

[0309] (10) Since a wide elastic material structure can be attained byforming the elastic structural material in a larger range over theentire circumference at least by more than the width of the protrusionson the outer circumference formed in the elastic structural material ascompared with the outer size of the semiconductor chip, protrusions onthe periphery of the elastic structural member are located outside ofthe semiconductor chip after the appending of the semiconductor chip,and it can be bonded substantially on the flat portion of the elasticstructural material, whereby the warping of the wiring substrate issuppressed. Further, since a large coating area of adhesive can beprovided, a not bonded portion caused by insufficient adhesive is lesslikely to occur, and the adhesive tends to extrude out uniformly aroundthe periphery of the semiconductor chip, so that a package of excellentmoisture proofness and reliability can be constituted with out applyingan additional peripheral sealing.

[0310] (11) In a case of forming the elastic structural material asdivided portions which are spaced so as to be not bonded on the externalterminals of the semiconductor chip, when each end of the spaces atwhich the divided elastic structural materials are opposed is formed asa grooved shape, the metal mask bridge portion can be restricted tonarrow the groove of the elastic structural material in thegroove-fillage technique of the elastic structural material, so that thegroove-fillage of the elastic structural material can be improved.

[0311] (12) If a plurality of grooves are formed at each of the ends ofthe elastic structural material, the strength of the groove-formingmetal mask can be improved.

[0312] (13) When a stopping dam for sealant flow is previously formed atthe grooves at each of the ends of the spaces at which the dividedstructural materials are opposed, the groove-fillage in the sealing stepcan further be improved.

[0313] (14) By previously forming stud bumps on the external terminalsof the semiconductor chip and connecting the external terminals of thesemiconductor chip and the wirings of the wiring substrate by way of thestud bumps, problems for in the bondability and the possibility ofdamage can be solved in the inner lead bonding technique, whereby thebondability is improved by the stud bumps and, further, the possibilityof damage can be prevented.

[0314] (15) By supplying the solder so as to previously surround thewirings of the wiring substrate and connecting the external terminals ofthe semiconductor chip and the external terminals of the wiringsubstrate by way of the solder, bondability can be improved and damagecan be suppressed in the bonding technique.

[0315] (16) By using the stud bumps, for example, made of solder or Auso as to surround the wirings of the wiring substrate, and by connectingthe wirings of the wiring substrate and the external terminals of thesemiconductor chip by way of the stud bumps, the bondability can beimproved and the possibility of damage can be suppressed in the bondingtechnique.

[0316] (17) By connecting the wirings of the wiring substrate and theexternal terminals of the semiconductor chip by using an Al, solder orAu wire, the problem, for example, of bondability or damage can besolved, and it is possible to attain connection by the concept of atypical wire bonding, not by the inner lead bonding, such as a TAB.

[0317] (18) By forming the lateral size of the wiring of the wiringsubstrate such that the size is gradually narrowed from the end of thesubstrate base material of the wiring substrate to the top end of thewiring and the lateral size is made constant from a predeterminedposition, and setting the size and the shape of the wiring such that thebending stress ratio a is from 1.2 to 1.5, since a suitable S-shapedconfiguration can be formed by merely driving down the bonding toolvertically with no return of the bonding tool, a lead of a stably shapedconfiguration can be formed without requiring a special soft-modifiedwire bonder; and, further, the contact time upon bonding can also beshortened since the trace of the bonding tool can be simplified.

[0318] (19) By using the electroconductive material as a core materialfor the wiring structure of the wiring substrate and applying only Auplating to the surface, since both the hardness and the brittleness ofthe lead are lowered as compared with a case of applying Ni-platingbetween the core material of the conductive material, such as Cu and Auplating, cracks are less likely in the lead itself, and damage to thesemiconductor chip at the counter bonding face can also be moderated.

[0319] (20) By forming the wirings on the rear face of the substratebase material of the wiring substrate, forming the insulation film onthe rear face of the wirings and disposing the elastic structurematerial on the rear face of the insulation film, since a rear facewiring insulation film structure can be obtained, direct contact of theelastic structural material with the wiring can be prevented and contactof the elastic structural material to the roughened surface of thesubstrate base material can also be prevented, so that bleeding of thelow molecular weight ingredients of the elastic structure material canbe suppressed and, further, the uneven wiring surface can be flattenedby coating the insulation film making it possible to avoiddisadvantages, such as the creation of voids upon forming the elasticstructural material.

[0320] (21) In the surface wiring structure, since the opening of theinsulation film is formed by defining the coating range of theinsulation film material, the fabrication accuracy for the hole diametercan further be improved as compared with a case of forming the openingby machining the substrate base material of the wiring substrate of therear face wiring structure.

[0321] (22) By setting the thickness of the insulation film bydetermining the coating condition for the insulation film material inthe surface wiring structure, since the film can be coated stably at afurther reduced thickness and the bump land disposed at a higher densitywith a small diameter can be formed as compared with the substrate basematerial, a smaller bump electrode can be joined more satisfactorily.

[0322] (23) In the surface wiring structure, since the pitch for thearrangement of the bump electrodes can be reduced as compared with therear face wiring structure, it is possible lo constitute a semiconductorpackage having output terminals at higher density.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor chip having a plurality of external terminals; a wiringsubstrate having a plurality of wirings and a plurality of broad wiringportions, wherein the wiring substrate is disposed over thesemiconductor chip, and has an opening positioned over the plurality ofexternal terminals; a first group of plural leads projecting inward ofthe opening, connecting the external terminals; and a second group ofplural leads projecting inward of the opening, not connecting theexternal terminals in the opening, wherein the first and second groupsof plural leads are connected with the plurality of broad wiringportions via the plurality of wirings, respectively, and wherein theplurality of broad wiring portions are wider than the plurality ofwirings and the first and second groups of plural leads, respectively.2. A semiconductor device according to claim 1 , further comprising: anelastic layer positioned between the wiring substrate and thesemiconductor chip, wherein the elastic layer has an opening positionedover the external terminals.
 3. A semiconductor device according toclaim 1 , further comprising: a plurality of bump electrodes positionedrespectively on a plurality of broad wiring portions connectingrespectively with the first group of plural leads via the plurality ofwirings.
 4. A semiconductor device according to claim 1 , furthercomprising: a plurality of bump electrodes positioned respectively onthe plurality of broad wiring portions.
 5. A semiconductor deviceaccording to claim 1 , wherein the plurality of broad wiring portionswhich are connected respectively with the second group of plural leadsvia the plurality of wirings are further connected with one of the firstgroup of plural leads via the plurality of wirings.
 6. A semiconductordevice according to claim 1 , wherein a plurality of broad wiringportions connected respectively with one of the second group of pluralleads via the plurality of wirings are further connected with anotherone of the second group of plural leads.
 7. A semiconductor deviceaccording to claim 1 , wherein interval pitch of a plurality of broadwiring portions connected respectively with the first group of pluralleads via the plurality of wirings is larger than that of the firstgroup of plural leads.
 8. A semiconductor device according to claim 1 ,wherein a distance between a plurality of broad wiring portionsconnecting respectively with the first group of plural leads via theplurality of wirings and an edge of the opening is different from adistance between a plurality of broad wiring portions connectedrespectively with the second group of plural leads via the plurality ofwirings and an edge of opening.
 9. A semiconductor device according toclaim 1 , wherein the opening has a first edge portion and a second edgeportion, opposed to the first edge portion, and wherein part of thefirst group of plural leads are protruding from the first edge andanother part of the first group of plural leads are protruding from thesecond edge.
 10. A semiconductor device according to claim 9 , whereinpart of the second group of plural leads are protruding from the firstedge, and another part of the second group of plural leads areprotruding from the second edge.
 11. A semiconductor device according toclaim 10 , wherein the part of the first group of plurality of leadsprotruding from the first edge are opposing to the other part of thesecond group of plural leads protruding from the second edge, andwherein the other part of the first group of plural leads protrudingfrom the second edge are opposing to the part of the second group ofplural leads protruding from the first edge.
 12. A semiconductor devicecomprising: a semiconductor chip having a plurality of externalterminals; a wiring substrate including a plurality of wirings, and aplurality of bump lands, the wiring substrate being disposed over thesemiconductor chip; a plurality of bump electrodes positioned onindividual ones of the bump lands, respectively; an elastic layerpositioned between the wiring substrate and the semiconductor chip,wherein an opening formed in the wiring substrate and the elastic layeris positioned over the plurality of external terminals, a first group ofplural leads projecting inward of the opening, connecting the externalterminals; and a second group of plural leads projecting inward of theopening, not connecting the external terminals in the opening, whereinthe first and second groups of plural leads are connected respectivelywith the plurality of bump lands via the plurality of wirings.
 13. Asemiconductor device according to claim 12 , wherein the bump lands arewider than the wirings.